(1) Field of the Invention
The present invention relates to method used to fabricate semiconductor devices, and more specifically to a method used to form dual gate dielectric layers for specific applications of complimentary metal oxide semiconductor (CMOS), devices, wherein one of the gate dielectric layers is a silicon nitride layer.
(2) Description of Prior Art
Advanced CMOS designs are formed for multiple applications with each application requiring a specific CMOS type device, in turn necessitating the fabrication of different type CMOS devices on the same semiconductor chip. For example CMOS devices such as a device used for input/output (I/O) applications require thicker gate insulator layers for I/O operation than counterpart CMOS devices used for core memory applications, which in turn are used at lower operating voltages thus requiring thinner gate insulator layers. Therefore to satisfy the requirements of the different CMOS applications dual gate oxide processes have been used. The conventional method of forming dual gate oxide layers is to initially grow the thick insulator component on an entire semiconductor substrate followed by removal of the thick insulator layer in the area of the semiconductor substrate requiring the thinner gate insulator layer. The thinner gate insulator layer is then regrown on the bare semiconductor region. However to insure quality of the regrown, thinner insulator layer, a pre-clean in a hydrofluoric acid containing solution should be used to remove native oxide from the region of the semiconductor substrate on which the thinner insulator layer will be regrown. If the pre-clean procedure is omitted the inclusion of the native oxide will degrade the quality of the regrown, thin insulator layer. However if the pre-clean procedure is employed the exposed thicker insulator layer will be thinned, perhaps to a point deleteriously influencing the performance or reliability of the I/O device featuring the thicker gate insulator component.
The present invention will describe a process for forming dual gate insulator layers in which a HF type pre-clean is applied prior to the formation of each gate insulator layer, made possible as a result of the insolubility of the exposed first gate insulator layer in the HF type solution. This allows for complete removal of native oxide from the surface of the semiconductor substrate prior to the growth of the second gate insulator layer, thus avoiding the inclusion of the lower dielectric quality native oxide in the second gate insulator layer. In addition this invention will describe a dual gate insulator process in which the thinner component is formed and exposed prior to formation of a thicker, second insulator layer. Prior art such as Okuno et al, in U.S. Pat. No. 6,110,842, Kepler, in U.S. Pat. No. 6,030,862, Tsui et al, in U.S. Pat. No. 5,960,289, Lutze et al, in U.S. Pat. No. 6,262,455 B1, and Buller et al, in U.S. Pat. No. 6,037,224, describe process sequences for attainment of dual gate insulator layers, however none of the prior art describe the unique process sequence described in this present invention in which dual gate insulator layers are formed using an HF type solution prior to formation of each component of the dual gate insulator layer.